Mitsubishi DS5000TK Guide de l'utilisateur

TABLE OF CONTENTSiSECURE MICROCONTROLLER USER’S GUIDE 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 1 Int

USER’S GUIDE050396 9/17310Watchdog TimerWhen the user’s software is being executed, the Watch-dog Timer can be used to automatically restart the pro-c

USER’S GUIDE050396 99/173100READ–MODIFY–WRITE INSTRUCTIONSMNEMONIC DESCRIPTIONANL – Logical ANDORL – Logical ORXRL – Logical Exclusive ORJBC – Branch

USER’S GUIDE050396 100/173101USE OF THE RPC MODE Figure 12–3P2.3/WRP2.2/RDP2.1/CEPORT 2P2.0/A0P2.7/DACKP2.6/DRQP2.5/IBFP2.4/OBFCONTROL BUSPORT 0P0.0/D

USER’S GUIDE050396 101/173102RPC STATUS REGISTER – STATUS (ADDRESS 0DAH) Figure 12–5ST7 ST6 ST5 ST4 IAO FO IBF OBFBit Description:RPS.7–4: General pur

USER’S GUIDE050396 102/173103RPC PROTOCOLData is written to the microprocessor by the host CPUand is placed in the DBBIN. At this time, the IBF flag

USER’S GUIDE050396 103/173104RPC CONTROL REGISTER – RPCTL (ADDRESS 0D8H) Figure 12–6RNR – EXBS AE IBI DMA RPCON RG0Bit Description:RPCTL.3: IBIWhen us

USER’S GUIDE050396 104/173105SECTION 13: PROGRAMMABLE TIMERSFUNCTIONAL DESCRIPTIONThe Secure Microcontroller incorporates two 16–bit tim-ers called T

USER’S GUIDE050396 105/173106TMOD.5, TMOD.4: Timer 1 Mode Control“Mode Select” These bit select the operating mode of the associated timer/counter as

USER’S GUIDE050396 106/173107Mode 0Figure 13–3 is a block diagram of a timer/counter oper-ating in Mode 0. Mode 0 configures either program-mable time

USER’S GUIDE050396 107/173108Mode 1Mode 1 for both programmable timers operates in anidentical fashion described for Mode 0, except Mode 1configures a

USER’S GUIDE050396 108/173109Mode 3When Timer 0 is selected for operation in Mode 3, bothTH0 and TL0 are configured independently as an 8–bittimer/cou

USER’S GUIDE050396 10/17311SECTION 4: PROGRAMMER’S GUIDEThe Secure Microcontroller uses nonvolatile RAMtechnology for both Program and Data memory.

USER’S GUIDE050396 109/173110SECTION 14: SERIAL I/OFUNCTION DESCRIPTIONThe Secure Microcontroller, like the 8051, includes apowerful Serial I/O (UART

USER’S GUIDE050396 110/173111value that generates the required time interval at itsoverflow. This is the most common mode of communi-cating with a PC

USER’S GUIDE050396 111/173112SCON.2: RB8“Rcv. Bit 8”: Indicates the state of the 9th data bit received while in Mode 2 or 3 operation.If Mode 1 is s

USER’S GUIDE050396 112/173113In most applications, Timer 1 will be configured as a tim-er which uses the internal clock oscillator frequency asits clo

USER’S GUIDE050396 113/173114was originally written into bit position D8. During the finalshift register operation, another 0 is shifted in from thele

USER’S GUIDE050396 114/173115MODE 0 BLOCK DIAGRAM AND TIMING Figure 14–2T1FLAGOUTPUT SHIFT REGISTERSI S0LOAD CLK D7 D6 D5 D4 D3 D2 D1 D0DATA BUSP3.0L

USER’S GUIDE050396 115/173116ASYNCHRONOUS OPERATIONMode 1, 2, and 3 provide asynchronous, full-duplexcommunication via the Serial I/O Port. The serial

USER’S GUIDE050396 116/173117ware. In an overrun condition with RI=1, the originally re-ceived word will remain in the Receive Data Buffer andall succ

USER’S GUIDE050396 117/173118SERIAL PORT MODE 1 BLOCK DIAGRAM Figure 14–3MUXTIMER 1OVERFLOW10T1FLAGBITDETECTORRXDPINDIV.BY16fCLK/2TRANSMIT TIMING:WRS

USER’S GUIDE050396 118/173119MODE2 AND 3 BLOCK DIAGRAM Figure 14–4T1FLAGBITDETECTORRXDPINDIV.BY16XMIT SHIFT REGISTERSI S0LOAD CLKDATA BUSP3.1LATCHTXD

7FH2FH2EH2DH2CH2BH2AH29H28H27H26H25H24H23H22H21H20H1FH18H17H10H0FH08H07H00HBANK 3BANK 2BANK 1BANK 0MSB LSB7F 7E 7D 7C 7B 7A 79 7877 76 75 74 73 72 71

USER’S GUIDE050396 119/173120APPLICATION: SERIAL PORTINITIALIZATIONThe serial port can provide either synchronous orasynchronous serial communication.

USER’S GUIDE050396 120/173121SM0 = 0 and SM1 = 1 corresponds to the value SCON.7= 0 and SCON.6 = 1. In addition the since the applica-tion requires r

USER’S GUIDE050396 121/173122This formula solves as :TH1 + 256 *2SMOD32 * 12 tCLK* BaudRateFor 9600 = Baud rate, TH1 = FDh with SMOD = 0.To create 19,

USER’S GUIDE050396 122/173123;This code example shows how to initialize the serial port and transmit /; receive code as described above.TA Equ 0C7hMCO

XTAL2XTAL1GNDNCEXT. OSC.SIGNALUSER’S GUIDE050396 123/173124SECTION 15: CPU TIMINGOSCILLATORThe Secure Microcontroller provides an on–chip oscilla-tor

USER’S GUIDE050396 124/173125INSTRUCTION TIMINGThe internal clocking signals are divided to produce thenecessary clock phases, state times, and machin

USER’S GUIDE050396 125/173126BYTE–WIDE RAM INSTRUCTION EXECUTION TIMING Figure 15–3S1P1 P2S2P1 P2S3P1 P2S4P1 P2S5P1 P2S6P1 P2S1P1 P2S2P1 P2S3P1 P2S4P

USER’S GUIDE050396 126/173127Multiplexed address and data information appear on thePort 0 pins as Program Memory fetches are performedon the Expanded

USER’S GUIDE050396 127/173128EXPANDED DATA MEMORY READ Figure 15–5PSENMACHINE CYCLE MACHINE CYCLEALEPORT 0PORT 2 PCH/P2 PCH/P2 DPH OR P2 OUT PCH/P2PCL

USER’S GUIDE050396 128/173129EXPANDED DATA MEMORY TIMINGThe timing for the Expanded Data Memory access cycleis illustrated in Figures 15–5 and 6. Acce

USER’S GUIDE050396 12/17313The 8051 instruction set allows efficient (single cycle)access to variables when using the Working Registers.These are a g

USER’S GUIDE050396 129/173130SECTION 16: PROGRAM LOADINGINTRODUCTIONProgram loading is performed to initialize the contentsof NV RAM and to configure

USER’S GUIDE050396 130/173131The indeterminate area contains various stacks andbuffers used by the loader, and a given byte in this areamay or may not

USER’S GUIDE050396 131/173132INVOKING AND EXITING THE LOADER ON THE DS5001/DS5002 SERIES Figure 16–1AUTOBAUD Routine:Awaits input on 1 of 3 channels –

USER’S GUIDE050396 132/173133SERIAL PROGRAM LOAD MODEThe Serial Bootstrap Loader provides the easiest meth-od of initially loading application softwar

USER’S GUIDE050396 133/173134AUTO–BAUD RATE DETECTIONThe Serial Bootstrap Loader has the capability of deter-mining which of the six supported baud ra

USER’S GUIDE050396 134/173135BOOTSTRAP LOADER INITIALIZATIONWhen loader mode is invoked, the device will await anincoming <CR> character at a va

USER’S GUIDE050396 135/173136An address will always be the right–most four digits of ahexadecimal number. For example, the following hexa-decimal numb

USER’S GUIDE050396 136/173137F byte [begin–address [end–address]]Fill memory with the value of the specified byte. An op-tional address range may be s

USER’S GUIDE050396 137/173138unaffected by this command.DS5001/DS5002:W [CRC/MCON/MSL/RPCTL] byteWrites byte to the requested register. The SL bit is

USER’S GUIDE050396 138/173139compared to the computed value for the record, and ifdifferent, the error message E:BADCKS is printed out.Unfortunately,

USER’S GUIDE050396 13/17314DS5000 Series Memory OrganizationAs mentioned above, the DS5000 series consists of theDS5000FP chip and the DS5000(T) and D

USER’S GUIDE050396 139/173140INTEL HEX FILE FORMAT8051–compatible assemblers produce an absolute out-put file in Intel Hex format. These files are com

USER’S GUIDE050396 140/173141PARALLEL PROGRAM LOAD OPERATIONThe DS5000 Parallel Program Load mode is compatiblewith the Program mode of the 87C51. The

USER’S GUIDE050396 141/173142PARALLEL PROGRAM LOAD MODETable 16–3 summarizes the selection of the availableParallel Program Load cycles. Figure 16–4 i

USER’S GUIDE050396 142/173143PARALLEL PROGRAMMING CONCERNSDallas Semiconductor highly recommends using theserial load mode for programming the DS5000.

USER’S GUIDE050396 143/173144SECTION 17: REAL–TIME CLOCKMany user applications require a time–of–day clock.For this reason, all Secure Microcontrolle

USER’S GUIDE050396 144/173145The timekeeper contains a shift register with 128 loca-tions. The first 64 locations correspond to a patternshown in Fig

USER’S GUIDE050396 145/173146PATTERN COMPARISON REGISTER DESCRIPTION Figure 17–27 654 321 010100011010111001100010100111010101000110101110011000101001

USER’S GUIDE050396 146/173147DS1215 REGISTER ENTRY FLOWCHART Figure 17–3Set ECE2 bit in the MCONregister to a logic 1Perform a dummy readoperation to

USER’S GUIDE050396 147/173148DS1215 TIME REGISTERS DESCRIPTION Figure 17–4OSC7 654 321 00.1 SEC00HR012/2400000000010 YEARRANGE (BCD)00–9900–5900–5901–

USER’S GUIDE050396 148/173149TIME REGISTER EXAMPLES Figure 17–57 654 321 000101000000000RANGE (BCD)00–9900–5900–5901–1201–0701–3101–1200–99CLOCK012345

USER’S GUIDE050396 14/17315DS5000 SERIES MEMORY MAP Figure 4–3BYTE–WIDE ACCESS WITH CE2(NONVOLATILE RAM)FFFFh7FFFh1FFFh0000PROGRAM DATA DATA= NO MEMOR

USER’S GUIDE050396 149/173150DS1283 WATCHDOG TIMEKEEPER CHIPThe DS2251T and DS2252T use the DS1283 Byte–wide RTC. This is also the clock of choice for

USER’S GUIDE050396 150/173151DS2251T/DS2252T RTC BLOCK DIAGRAM Figure 17–6DS5001CPUDS1283RTCDS2251TVCCOVCCPE1 CER/W WEBA5–0 A5–0BD7–0INTBINTAINTPDS50

USER’S GUIDE050396 151/173152DS1283 REAL–TIME CLOCK MEMORY MAP Figure 17–7 0.1 SECONDS 0.01 SECONDS0 10 SECONDS SECONDSMINUTES10 MINUTES0M 10 MIN ALAR

USER’S GUIDE050396 152/173153The time, calendar, and alarms are controlled by theinformation in these 14 registers. In particular, the Com-mand regis

USER’S GUIDE050396 153/173154DS1283 RTC INTERRUPTSThe DS1283 provides two interrupt functions. They aretime–of–day alarm and a watchdog alarm. The w

USER’S GUIDE050396 154/173155APPLICATION: USING THE DS5000T RTC(DS1215 EXAMPLE)The DS5000T and DS2250T use the DS1215 PhantomTime Chip RTC. This clo

USER’S GUIDE050396 155/173156lcall CLOSE ;Close date/time registers.mov IE, #0mov TMOD, #20H ;Initialize themov TH1, #0FAH ;serial portmov TL1, #0FAH

USER’S GUIDE050396 156/173157OPEN: LCALL CLOSE ;Make sure it is closed.MOV B,#4 ;Set pattern period count.MOV A,#0C5H ;Load first byte of pattern.OPEN

USER’S GUIDE050396 157/173158POP DPH ;Restore the dataPOP DPL ; pointer from stack.RET ;Return.;;************************************;*** SUBROUTINE T

USER’S GUIDE050396 158/173159APPLICATION: USING THE DS2251T RTC(DS1283 EXAMPLE)The DS2251T or DS2252T use the DS1283 Byte–widetype real–time clock (R

USER’S GUIDE050396 15/17316case is to select a Range of 8K, and to choose a Parti-tion of greater than 8K. This will result in the Range asthe limitin

USER’S GUIDE050396 159/173160;Set Time CLR A MOV R0, #0Bh LCALL WBYTE ; Freeze the regi

USER’S GUIDE050396 160/173161 LCALL RBYTE ; Read the day of month. ANL A, #3FH ; Isolate it.

USER’S GUIDE050396 161/173162 ORL A, B MOV B, A SJMP HEX_LP;HEX_OUT: MOV B,

USER’S GUIDE050396 162/173163 POP MCON ; Restore MCON register. RET ; Return.;YEAR:

USER’S GUIDE050396 163/173164SECTION 18: TROUBLESHOOTINGDallas Semiconductor’s Secure Microcontroller familyhas proven itself to be a reliable and ea

USER’S GUIDE050396 164/173165lithium batteries have a very long time constant. Puttingthe device on the shelf for one to two weeks may restoreenough v

USER’S GUIDE050396 165/173166HIGH CURRENT DRAIN IN STOP MODESecure Microcontrollers draw approximately 80 µA ofICC in Stop mode. However, the EA pin

USER’S GUIDE050396 166/173167Battery backed signalsDo not connect lithium backed chip enables or signals tonon–backed devices. This produces a drain o

USER’S GUIDE050396 167/173168SECTION 19: INSTRUCTION SET DETAILSMNEMONICINSTRUCTION CODEHEXBYTECYCLEEXPLANATIONMNEMONICD7D6D5D4D3D2D1D0HEX BYTE CYCLE

USER’S GUIDE050396 168/173169EXPLANATIONCYCLEBYTEHEXINSTRUCTION CODEMNEMONIC EXPLANATIONCYCLEBYTEHEXD0D1D2D3D4D5D6D7MNEMONICARITHMETIC OPER.DA A 1 1 0

USER’S GUIDE050396 16/17317MCON.3: RA32/8“Range Address”: Sets the maximum usable address on the Byte–wide bus.RA32/8 = 0 sets Range Address = 1FFFH (

USER’S GUIDE050396 169/173170EXPLANATIONCYCLEBYTEHEXINSTRUCTION CODEMNEMONIC EXPLANATIONCYCLEBYTEHEXD0D1D2D3D4D5D6D7MNEMONICRL A 0 0 1 0 0 0 1 1 23 1

USER’S GUIDE050396 170/173171EXPLANATIONCYCLEBYTEHEXINSTRUCTION CODEMNEMONIC EXPLANATIONCYCLEBYTEHEXD0D1D2D3D4D5D6D7MNEMONICMOV direct,#data0a7d71a6d6

USER’S GUIDE050396 171/173172EXPLANATIONCYCLEBYTEHEXINSTRUCTION CODEMNEMONIC EXPLANATIONCYCLEBYTEHEXD0D1D2D3D4D5D6D7MNEMONICCLR C 1 1 0 0 0 0 1 1 C3 1

USER’S GUIDE050396 172/173173EXPLANATIONCYCLEBYTEHEXINSTRUCTION CODEMNEMONIC EXPLANATIONCYCLEBYTEHEXD0D1D2D3D4D5D6D7MNEMONICACALL addr 11 a10a7a9a6a8a

USER’S GUIDE050396 173/173174EXPLANATIONCYCLEBYTEHEXINSTRUCTION CODEMNEMONIC EXPLANATIONCYCLEBYTEHEXD0D1D2D3D4D5D6D7MNEMONICJNB bit, rel 0b7r70b6r61b5

USER’S GUIDE050396 17/17318a Partitionable mode (PM=0), the DS5001 can use upto 64K x 8 SRAM for program and data on its Byte–widebus. It can partitio

USER’S GUIDE050396 18/17319PARTITIONABLE MEMORY MAP FOR DS5001/DS5002 SERIES Figure 4–5FFFFh0000PROGRAM DATALEGEND:BYTE–WIDEBUS ACCESSBYTE–WIDEBUS ACC

USER’S GUIDE050396 1/1732SECTION 1: INTRODUCTIONThe Secure Microcontroller family is a line of8051–compatible devices that utilize nonvolatile RAM(NV

USER’S GUIDE050396 19/17320Any address that does not fall into the Byte–wide busarea is routed to the Expanded bus of Ports 0 and 2. Thiscould only oc

USER’S GUIDE050396 20/17321On occasion, a memory mapped peripheral is neededthat interfaces directly to an 8051 multiplexed bus.When this occurs, MOVX

USER’S GUIDE050396 21/17322DS5001/DS5002 SERIES MCON REGISTER Figure 4–8PA3 PA2 PA1 PA0 RG1 PES PM –––Bit Description:MCON.7–4: PA3–0Partition Address

USER’S GUIDE050396 22/17323DS5001/DS5002 SERIES RPCTL REGISTER BITS AFFECTING MEMORY Figure 4–9RNR ––– EXBS AE IBI DMA RPCON RG0Bit Description:RPCTL.

USER’S GUIDE050396 23/17324Application software always has unrestricted read/writeaccess to the nonvolatile RAM designated as datamemory. This is the

USER’S GUIDE050396 24/17325MOV TA, #0AAh ; TIMED ACCESSMOV TA, #55h ; TIMED ACCESS 2MOV MCON, #10001010b ; SET PAA BIT. ; USER’S CODE TO LOAD. ; RAM

USER’S GUIDE050396 25/17326SOFT RELOAD OF A DS5001/DS5002When application software decides that it should repro-gram a portion of memory, the softwar

USER’S GUIDE050396 26/17327MOV TA, #0AAh ; TIMED ACCESSMOV TA, #55h ; TIMED ACCESS 2MOV MCON, #00011000b ; SET PARTITION TO 1000h| ; USER’S CODE TO L

USER’S GUIDE050396 27/17328Special Function RegistersThe Secure Microcontroller uses Special Function Reg-isters (SFRs) to control most functions. In

F7 F6 F5 F4 F3 F2 F1 F0E7 E6 E5 E4 E3 E2 E1 E0C AC F0 RS1 RS0 OV PD7 D6 D5 D4 D3 D2 D1 D0PA3 PA2 PA1 PA0 RA32/8 ECE2PAASLRWT PS PT1 PX1 PT0 PX0BF – –

USER’S GUIDE050396 2/1733LARGE NONVOLATILE MEMORYSoft Microprocessor chips provide nonvolatile memorycontrol for standard CMOS SRAM. Modules combineth

C/TC/TC/TWTRPORDIRECT BYTEADDRESSSPECIAL FUNCTIONREGISTER SYMBOL(MSB) (LSB)BIT ADDRESSF7 F6 F5 F4 F3 F2 F1 F0E7 E6 E5 E4 E3 E2 E1 E00F0H0E0HNOT BIT AD

USER’S GUIDE050396 30/17331POWER CONTROL REGISTERLabel: PCON Register Address: 087HD7 D6 D5 D4 D3 D2 D1 D0SMOD POR PFW WTR EPFW EWT STOP IDLBit Descr

USER’S GUIDE050396 31/17332PCON.3: EPFW“Enable Power Fail Interrupt”: Used to enable or disable the Power Fail Interrupt. When EPFW is set to a 1,it w

USER’S GUIDE050396 32/17333TIMER CONTROL REGISTERLabel: TCON Register Address 088HD7 D6 D5 D4 D3 D2 D1 D0TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Bit Descripti

USER’S GUIDE050396 33/17334TCON.0: IT0“Interrupt 0 Type Select”: When set to 1, 1–to–0 transitions on INT0 will be used to generate interruptrequests

USER’S GUIDE050396 34/17335SERIAL CONTROL REGISTERLabel:SCON Register Address: 098HD7 D6 D5 D4 D3 D2 D1 D0SM0 SM1 SM2 REN TB8 RB8 TI RIBit Descriptio

USER’S GUIDE050396 35/17336Initialization: Cleared to a 0 on any type of reset.SCON.0: RI“Receive Interrupt”: Status bit used to signal that a serial

USER’S GUIDE050396 36/17337INTERRUPT PRIORITY REGISTERLabel:IP Register Address: 0B8HD7 D6 D5 D4 D3 D2 D1 D0RWT – – PS PT1 PX1 PT0 PX0Bit Description

USER’S GUIDE050396 37/17338DS5001 CRC REGISTERLabel: CRC Register Address: 0C1HRNGE3 RNGE2 RNGE1 RNGE0 ––– ––– MDM CRCBit Description:CRC.7–4 RNGE3–

USER’S GUIDE050396 38/17339DS5000 MEMORY CONTROL REGISTERLabel:MCON Register Address: 0C6HD7 D6 D5 D4 D3 D2 D1 D0PA3 PA2 PA1 PA0 RA32/8 ECE2 PAA SLBi

USER’S GUIDE050396 3/1734PRODUCT DESCRIPTIONAll devices listed below have the standard 8051 familyfeature set listed once here for convenience, but no

USER’S GUIDE050396 39/17340Read Access: May be read normally anytime.Write Access: Cannot be modified by the application software; can only be written

USER’S GUIDE050396 40/17341Write Access: Timed Access Protected. Cannot be written by the application software ifset to 0000B by the serial loader.

USER’S GUIDE050396 41/17342PROGRAM STATUS WORD REGISTERLabel:PSW Register Address: 0D0HD7 D6 D5 D4 D3 D2 D1 D0C AC F0 RS1 RS0 OV PAll of the bits in

USER’S GUIDE050396 42/17343DS5001/DS5002 RPC CONTROL REGISTERLabel: RPCTL Register Address: 0D8HRNR ––– EXBS AE IBI DMA RPCON RG0Bit Description:RPC

USER’S GUIDE050396 43/17344Read Access: Can be read anytime.Write Access: Can be written when the RPC mode is enabled (RPCON=1).RPCTL.1 RPCONEnable th

USER’S GUIDE050396 44/17345Read Access: Can be read by DS5001/DS5002 and host CPU when in RPC mode.Write Access: Can be written by the DS5001/DS5002 w

USER’S GUIDE050396 45/17346INSTRUCTION SETIntroductionThe Secure Microcontroller executes an instruction setwhich is object code compatible with the i

USER’S GUIDE050396 46/17347The 16–bit DPTR register may be used to access anyData Memory location within the 64K byte space.MOVX @DPTR,A ; Load the Da

USER’S GUIDE050396 47/17348Program Status FlagsAll of the Program Status flags are contained in the PSWregister. Instructions which affect the states

USER’S GUIDE050396 48/17349SECTION 5: MEMORY INTERCONNECTThe Secure Microcontroller family is divided betweenchips and modules. This sections illustra

USER’S GUIDE050396 4/1735DS2251T 128K Soft Microcontroller ModuleThe DS2251T is a SIMM based on the DS5001. It pro-vides up to 128K bytes of on–board

REAL TIME CLOCK(OPTION)32K X 8 SRAMDS5000FPDS5000(T), DS2250(T)40–PINS(8)(8)(8)(8)VCCPORT0PORT1PORT2PORT3ALEPSENEARSTXTAL1XTAL2GNDVCCOADDRDATACE1CE2VL

VCCOR/WCE1BA14–BA0BD7–BD0MSELCE2VCCVLIPORT0PORT1PORT2PORT3GND28272014VCCWECSA14–A0D7–D0GNDOE32K x 8 SRAMVCCWECSA14–A0D7–D0GNDOE32K x 8SRAM28272014VCCW

28272014282720142827201428272014222222221210742636214+5V1354+3V52DS5001FP/DS5002FP+5VVCCVLIPORT0PORT1PORT2PORT3GNDVCCOR/WCE1BA14–BA0BD7–BD0CE2CE3CE4MS

USER’S GUIDE050396 52/17353MEMORY INTERCONNECT USING THE 128K SRAM Figure 5–51354+3v+5v12107428272022161452DS5001FP/DS5002FPVCCWECS1A16A15A14–A0D7–D0G

USER’S GUIDE050396 53/17354DS2251T–128 BLOCK DIAGRAM Figure 5–6DS2251TDS5001FP 128K X 8 SRAMREAL TIME CLOCKBYTE–WIDE ADDRESS BUSBYTE–WIDE DATA BUS(14)

USER’S GUIDE050396 54/17355DS2252T–32 BLOCK DIAGRAM Figure 5–7DS2252TDS5002FP 32K X 8 SRAMREAL TIME CLOCK(8)(8)(8)(8)+3VVLIVCCPORT0PORT1PORT2PORT3ALER

USER’S GUIDE050396 55/17356SECTION 6: LITHIUM/BATTERY BACKUPSoft Microcontroller devices are lithium backed for dataretention in the absence of VCC.

USER’S GUIDE050396 56/17357POWER SUPPLY SLEW RATE Figure 6–140 µs, 130 µsVCCVCCMINVLILITHIUMCURRENTEach time VCC is restored, the lithium backed funct

USER’S GUIDE050396 57/1735810 years depending on the user’s actual environmentand design goals.The system lifetime can be determined from threeparamet

USER’S GUIDE050396 58/17359LITHIUM BATTERY USAGEIn the vast majority of applications, lithium batteries pro-vide a reliable means of backing up data a

USER’S GUIDE050396 5/1736SECTION 2: SELECTION GUIDEThe following configurations are available. Speeds arerated maximums, but all members of the Secure

USER’S GUIDE050396 59/17360SECTION 7: POWER MANAGEMENTIntroductionAll Dallas Semiconductor microcontrollers are imple-mented using fully static CMOS

USER’S GUIDE050396 60/17361Write Access: Cannot be written.PCON.3: EPFW“Enable Power Fail Interrupt”: Used to enable or disable the Power Fail Interru

USER’S GUIDE050396 61/17362The original contents of those Special Function regis-ters that are initialized by a reset are lost.Voltage Monitoring Circ

USER’S GUIDE050396 62/17363Power Fail InterruptWhen VCC is stable, program execution proceeds asnormal. If VCC should decay from its nominal operating

USER’S GUIDE050396 63/17364threshold, the Power On Reset cycle will be executed asbefore. As a result, no special processing is required insoftware to

USER’S GUIDE050396 64/17365SECTION 8: SOFTWARE CONTROLIntroductionSeveral features have been incorporated into theSecure Microcontroller to help insur

USER’S GUIDE050396 65/17366This code allows the reset of the Watchdog Timer:MOV 0C7H,#0AAH ; 1st TA ValueMOV 0C7H,#055H ; 2nd TA Value 2 CyclesSETB IP

USER’S GUIDE050396 66/17367Timed Access provides a statistical protection. It isunlikely that randomly generated states will correctlymatch the sequen

USER’S GUIDE050396 67/17368During subsequent program execution, the WatchdogTimer can be reset by a Timed Access write operationwhich sets the RWT bit

USER’S GUIDE050396 68/17369WATCHDOG TIMER CONTROL BITSBit Description:PCON.4: WTR“Watchdog Timer Reset” Set to a 1 when a Watchdog Timer timeout occur

USER’S GUIDE050396 6/1737SECTION 3: SECURE MICROCONTROLLERARCHITECTUREIntroductionThe Secure Microcontroller family is based on an 8051compatible core

USER’S GUIDE050396 69/17370blocks over which the CRC calculation is performed.For example, if the nibble is set to 0001b, the CRC rangeis from 0000 to

USER’S GUIDE050396 70/17371CRC CODE EXAMPLE Figure 8–3This routine tests the CRC–16 circuit in the DS5001FPcrcmsb equ 0C3hcrclsb equ 0C2horg 00h ;afte

USER’S GUIDE050396 71/17372SECTION 9: FIRMWARE SECURITYOne of the most unique features of the Secure Micro-controller is its firmware security. The f

USER’S GUIDE050396 72/17373SECURITY LOCKOrdinarily, the easiest way to dump (view) the memorycontents of a Secure Microcontroller is using the Boot-st

USER’S GUIDE050396 73/17374DS5000 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 9–1PROGRAMCOUNTERDATAPOINTERADDRESSENCRYPTOREXTERNALBYTEWIDERAM40–BIT ENCRY

USER’S GUIDE050396 74/17375In a DS5000, the encryption feature is optional. ADS5000 can be locked irrespective of its encryption andencrypted irrespe

USER’S GUIDE050396 75/17376Encryption AlgorithmThe Secure Microcontroller family uses a proprietaryalgorithm to encrypt memory. The DS5000FP andDS5002

CE1ALEBA14–0BD7–0XXXXh YYYYh QQQQh RRRRhSINGLE CYCLE INSTRUCTION SINGLE CYCLE INSTRUCTIONENCRYPTED MEMORY ACCESS WITH DUMMY FETCHESEither XXXX or YYYY

USER’S GUIDE050396 77/17378On–chip Vector RAMA 48–byte RAM area is incorporated inside theDS5000FP and DS5002FP. This area maps to the first48 locatio

USER’S GUIDE050396 78/17379Security Summary by PartThe preceding information outlined each of the securityfeatures. Their inclusion in various parts i

USER’S GUIDE050396 7/1738SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 3–1158CE1CE2R/WADDRESSENCRYPTORDATAENCRYPTORTIMING ANDCONTROLTAMCO

USER’S GUIDE050396 79/17380APPLICATION: ADVANCED SECURITYTECHNIQUESThe Secure Microcontroller family has been used fornumerous applications requiring

USER’S GUIDE050396 80/17381Change CodePerhaps most importantly, the user should reprogramportions of the Secure Microcontroller that deal with se-curi

USER’S GUIDE050396 81/17382SECTION 10: RESET CONDITIONSReset SourcesThe Secure Microcontroller family is designed to pro-vide proper reset operation

USER’S GUIDE050396 82/17383SPECIAL FUNCTION REGISTER RESET STATES Table 10–1REGISTER LOCATION RESET CONDITION RESET TYPEPC N/A 0000h AllACC E0h 00h Al

USER’S GUIDE050396 83/17384Power On ResetThe Secure Microcontroller family provides an internalPower On Reset capability which requires no externalcom

USER’S GUIDE050396 84/17385No–VLI Power On ResetDuring a Power On Reset cycle, a test is automaticallyperformed by the internal control circuitry to m

USER’S GUIDE050396 85/17386APPLICATION: RESET ROUTINE EXAMPLELike the 8051, Dallas Semiconductor Microcontrollerswill begin execution at address 0000h

USER’S GUIDE050396 86/17387A code example that initializes the memory map is asfollows. It assumes that the DS5000FP user requires aPartition of 5800h

USER’S GUIDE050396 87/17388TimersThe microprocessor disables timer activity (excludingthe Watchdog) and serial port communication on a re-set. Therefo

USER’S GUIDE050396 88/17389SECTION 11: INTERRUPTSThe Secure Microcontroller family follows the standard8051 convention for interrupts (with one extra

USER’S GUIDE050396 8/1739Parallel I/OFour SFR’s provide access for the four parallel I/O portlatches. These I/O ports are denoted as P0, P1, P2, andP3

USER’S GUIDE050396 89/17390External InterruptsThe two external interrupts are INT0 and INT1. Theycorrespond to P3.2 and P3.3 respectively. These pinsb

USER’S GUIDE050396 90/17391global enable bit. It can only be enabled or disabledusing the EPFW bit.Simulated InterruptsExcept for PFW, any interrupt c

USER’S GUIDE050396 91/17392INTERRUPT ENABLE CONTROL BITS Figure 11–2Bit Description:All bits are read/write at any time and are cleared to 0 following

USER’S GUIDE050396 92/17393INTERRUPT PRIORITIESThe Secure Microcontroller provides a three priorityinterrupt scheme. Multiple priority levels allow hi

USER’S GUIDE050396 93/17394INTERRUPT ACKNOWLEDGEThe various interrupt flags are sampled an latched onceevery machine cycle, specifically during clock

USER’S GUIDE050396 94/17395cycle. If the interrupt acknowledge does not take placefor one of the reasons cited above, the request flag willbecome subs

EXTERNALADDRESSCONTROLVCCADDRESS/DATAPOWERDOWNPORT0.nINTERNALDATA BUSWRITEENABLEREADENABLEREADLATCH/PINDQQUSER’S GUIDE050396 95/17396SECTION 12: PARA

USER’S GUIDE050396 96/17397PORT 1 FUNCTIONAL CIRCUITRYVCCPOWERDOWNPORT0.nINTERNALDATA BUSWRITEENABLEREADENABLEREADLATCH/PINDQVCCVCCDELAY= 2TclkQPORT 2

USER’S GUIDE050396 97/17398PORT 3 FUNCTIONAL CIRCUITRYVCCPOWERDOWNPORT3.nWRITEENABLEREADENABLEREADLATCH/PINDQVCCVCCSERIAL I/O AND EXTERNALMEMORY CONTR

USER’S GUIDE050396 98/17399least significant eight bits of address and data. When 1’sare output on Port 2 for address bits during these cycles,strong