Mitsubishi DS5000TK Guide de l'utilisateur Page 141
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
USER’S GUIDE
050396 140/173
141
PARALLEL PROGRAM LOAD OPERATION
The DS5000 Parallel Program Load mode is compatible
with the Program mode of the 87C51. The hardware
configuration used for this mode of operation is shown in
Figure 16–3. Dallas Semiconductor recommends the
use of the serial Program Load Mode over the Parallel
Program Load Mode because of the ease of imple-
mentation and simpler hardware interface.
PARALLEL PROGRAM LOAD CONFIGURATION Figure 16–3
ALE/PROG
PSEN
RST
D7–D0
A15–A12 PROGRAM ADDRESS
PROGRAM DATA IN/
VERIFY DATA OUT
A7–A0
A11–A8
PROGRAM
ADDRESS
PROGRAM
CONTROL
V
CC
GND
DS5000
P1.7–
P1.0
P2.3–
P2.0
EA/V
PP
P2.7
P2.6
P2.5
XTAL1
XTAL2
P0.7–
P0.0
P3.7–
P3.4
PARALLEL PROGRAM LOAD CYCLES Figure 16–4
ALE/PROG
ADDRESS
DATA IN
ADDRESS
DATA OUT
PROGRAM CYCLE VERIFY CYCLE SECURITY SET
CYCLE
P2.3–P2.0
P1.7–P1.0
PORT 0
EA/V
PP
P2.7
P2.6
V
PP
V
IH
- TABLE OF CONTENTS 1
- SECTION 1: INTRODUCTION 2
- SOFTWARE SECURITY 2
- SEPARATE ADDRESS/DATA BUS 2
- LARGE NONVOLATILE MEMORY 3
- IN–SYSTEM LOADING 3
- HIGH RELIABILITY OPERATION 3
- PRODUCT DESCRIPTION 4
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- SECTION 2: SELECTION GUIDE 6
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- INTERNAL DATA BUS 8
- INTERNAL ADDRESS BUS 8
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- Watchdog Timer 10
- Resident Loader ROM 10
- Secure Microcontroller Memory 11
- Organization 11
- Internal Registers 11
- Programmer’s note 12
- Program and Data Memory 13
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- DS5000 Memory Map Control 16
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- 050396 17/173 18
- DS5001/DS5002 Memory Mapped 20
- Peripherals 20
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- 050396 25/173 26
- Special Function Registers 28
- PA3 PA2 PA1 PA0 RA32/8 ECE2 29
- POWER CONTROL REGISTER 31
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- TIMER CONTROL REGISTER 33
- TIMER MODE REGISTER 34
- SERIAL CONTROL REGISTER 35
- INTERRUPT ENABLE REGISTER 36
- INTERRUPT PRIORITY REGISTER 37
- DS5001 CRC REGISTER 38
- DS5001 MCON REGISTER 40
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- PROGRAM STATUS WORD REGISTER 42
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- INSTRUCTION SET 46
- Introduction 46
- Addressing Modes 46
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- Program Status Flags 48
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- DATA RETENTION 56
- BATTERY BACKED CIRCUITS 56
- BATTERY ATTACH PROCEDURE 57
- BATTERY LIFETIME 57
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- LITHIUM BATTERY USAGE 59
- FRESHNESS SEAL 59
- SECTION 7: POWER MANAGEMENT 60
- Idle Mode 60
- Stop Mode 61
- Voltage Monitoring Circuitry 62
- Power Fail Interrupt 63
- Total Power Failure 63
- Partial Power Failures 63
- SECTION 8: SOFTWARE CONTROL 65
- Timed Access 65
- TIMED ACCESS Figure 8–1 65
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- WATCHDOG TIMER Figure 8–2 68
- WATCHDOG TIMER CONTROL BITS 69
- CRC MEMORY VERIFICATION 69
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- CRC CODE EXAMPLE Figure 8–3 71
- SECTION 9: FIRMWARE SECURITY 72
- SECURITY OVERVIEW 72
- SECURITY LOCK 73
- RAM Memory 73
- Encrypted Memory 73
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- Encryption Algorithm 76
- Encryption Key 76
- Dummy Bus Access 77
- On–chip Vector RAM 78
- Self–Destruct Input 78
- Microprobe/Die Top Coating 78
- Random Number Generator 78
- Security Summary by Part 79
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- Change Code 81
- External Circuits 81
- Tamper Protection 81
- SECTION 10: RESET CONDITIONS 82
- Reset Sources 82
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- Power On Reset 84
- Power On Reset 85
- External Reset 85
- Watchdog Timer Reset 85
- Memory Map 86
- Interrupts 87
- Protection 88
- SECTION 11: INTERRUPTS 89
- INTERRUPT SOURCES 89
- External Interrupts 90
- Timer Interrupts 90
- Serial Port Interrupts 90
- Power–fail Warning Interrupt 90
- Simulated Interrupts 91
- INTERRUPT PRIORITIES 93
- INTERRUPT ACKNOWLEDGE 94
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- SECTION 12: PARALLEL I/O 96
- OVERVIEW 96
- PORT 1 FUNCTIONAL CIRCUITRY 97
- PORT 2 FUNCTIONAL CIRCUITRY 97
- PORT 3 FUNCTIONAL CIRCUITRY 98
- OUTPUT FUNCTIONS 98
- INPUT FUNCTION 99
- REPROGRAMMABLE PERIPHERAL 100
- CONTROLLER (RPC) 100
- RPC INTERRUPTS 101
- Bit Description: 102
- RPC PROTOCOL 103
- DMA OPERATION 103
- FUNCTIONAL DESCRIPTION 105
- Bit Description 105
- USER’S GUIDE 106
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- SECTION 14: SERIAL I/O 110
- FUNCTION DESCRIPTION 110
- SCON.2: RB8 112
- SCON.1: TI 112
- SCON.0: RI 112
- BAUD RATE GENERATION 112
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- 050396 113/173 114
- TRANSMIT TIMING: 115
- RECEIVE TIMING: 115
- ASYNCHRONOUS OPERATION 116
- Mode 2 and 3 117
- APPLICATION: SERIAL PORT 120
- INITIALIZATION 120
- SERIAL I/O OPERATING MODES 120
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- 050396 121/173 122
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- SECTION 15: CPU TIMING 124
- OSCILLATOR 124
- INSTRUCTION TIMING 125
- EXPANDED DATA MEMORY TIMING 129
- SECTION 16: PROGRAM LOADING 130
- INTRODUCTION 130
- INVOKING THE BOOTSTRAP LOADER 130
- DS5000 Series 131
- DS5001/DS5002 Series 131
- EXITING THE LOADER 131
- SERIAL PROGRAM LOAD MODE 133
- AUTO–BAUD RATE DETECTION 134
- COMMAND LINE INTERFACE 135
- COMMAND LINE SYNTAX 135
- COMMAND SUMMARIES 136
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- Xon/Xoff 138
- DS5002FP COMMANDS 138
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- INTEL HEX FILE FORMAT 140
- PARALLEL PROGRAM LOAD MODE 142
- PARALLEL PROGRAMMING CONCERNS 143
- RPC PROGRAM MODE OPERATION 143
- SECTION 17: REAL–TIME CLOCK 144
- DS1215 PHANTOM TIME CHIP 144
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- REGISTERS 148
- SPECIAL BITS 148
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- MEMORY MAP 151
- TIME–OF–DAY ALARM 152
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- DS1283 RTC INTERRUPTS 154
- (DS1215 EXAMPLE) 155
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- 050396 156/173 157
- 050396 157/173 158
- (DS1283 EXAMPLE) 159
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- SECTION 18: TROUBLESHOOTING 164
- UNEXPLAINED DEVICE RESETS 164
- WRONG TIME 164
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- OGRAM BRANCHING 174
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